Volume 7 Issue 3 - September 2016

  • 1. Reduction in area and power analysis with d-latch enabled carry select adder using gate diffusion input

    Authors : Sakshi Bhatnagar, Vimal Agarwal

    Pages : 427-434

    DOI : http://dx.doi.org/10.21172/1.73.556

    Keywords : Gate Diffusion Input (GDI)Carry Select Adder (CSA)Binary to Excess-1 Converter (BEC-1)

    Abstract :

    Arithmetic operation addition is the most frequently used in micro-processors, signal processors of digital computers. It acts as a back bone for the combination of other arithmetic operations like subtraction, multiplication. Therefore, for the proficient execution of any arithmetic unit, the adder configuration has become an important hardware unit. There exists a vast variety of circuit architectures with different parameters and performance characteristics which are widely used in the practice. VLSI designs require compact area and low power systems. The overall area reduction of the system is decided at all the level of its architecture, fabrication designs, logic gates design, optimization of circuits, gate clocking , layout etc. In this paper, Carry select adders are implemented using BEC-1 and D-Latch with Gate Diffusion Input (GDI) using TANNER software tool and are compared in terms of Area and Power Utilization.

    Citing this Journal Article :

    Sakshi Bhatnagar, Vimal Agarwal, "Reduction in area and power analysis with d-latch enabled carry select adder using gate diffusion input", https://www.ijltet.org/journal_details.php?id=907&j_id=3374, Volume 7 Issue 3 - September 2016, 427-434, #ijltetorg