Volume 10 Issue 3 - May 2018

  • 1. Design and implementation of 3-bit flash analog to digital converter (adc)

    Authors : Prof. Jayashree C Nidagundi, Sunita S Bettakusugal

    Pages : 208-214

    DOI : http://dx.doi.org/10.21172/1.103.36

    Keywords : -ADC, sample and hold(S/H) circuit, TMCC, Threshold voltage, Multiplexer, encoder and Flash ADC.

    Abstract :

    Analog to Digital converters are essential in all communication and signal processing applications. Among all ADC’S Flash ADC has a high speed conversion rate. It has a capacity of sampling a signal up to Giga Bites. The conventional Flash ADC contains the resistor ladder network, comparator, and encoder. Due to the use of resistor ladder network in conventional Flash ADC static power consumption is more to overcome this issue, new 3-Bit Flash ADC has been proposed. The proposed ADC is consists of sample and hold (S/H) circuit, threshold modified comparator circuit and priority encoder. The design is implemented using cadence virtuoso schematic tool under cadence 180nm Technology with a supply voltage of 1.8 V and clock frequency of 1M Hz. Simulation is carried using cadence spectre simulator tool.

    Citing this Journal Article :

    Prof. Jayashree C Nidagundi, Sunita S Bettakusugal, "Design and implementation of 3-bit flash analog to digital converter (adc)", https://www.ijltet.org/journal_details.php?id=932&j_id=4626, Volume 10 Issue 3 - May 2018, 208-214, #ijltetorg