Volume 10 Issue 2 - April 2018

  • 1. Design and analysis of pd-pwm multilevel inverter with reduced switch count

    Authors : V.sivanesan, Dr.c.christoberasir Rajan

    Pages : 89-95

    DOI : http://dx.doi.org/10.21172/1.102.14

    Keywords : Multilevel Inverter (MLI); Phase Disposition (PD); Pulse Width Modulation (PWM); Total Harmonic Distortion (THD)

    Abstract :

    This study proposes a single-phase, 9-level, multilevel inverter (MLI) topology. The multicarrier, Phase Disposition (PD) Pulse Width Modulation (PWM) scheme is employed to generate the gating signals for the power switches. By controlling the modulation index, the desired number of levels: 3, 5, 7 and 9 of the inverter’s output voltage can be achieved. For modulation index of: 0.2, 0.4, 0.6 and 0.8, the proposed inverter configuration was subjected to an R–L load and the respective numbers of output voltage level were synthesized. The topology is self-voltage balanced across the series connected capacitors. The proposed approach helps in reducing the number of independent dc voltage sources. Also the harmonic content in the output voltage is very less when compared with conventional topologies. For a modulation index of 0.8, a Total Harmonic Distortion value of 14.03% has been achieved. To verify the performance of the proposed inverter architecture, simulations and experiments are carried out on inverter for an R–L load; and adequate results are presented.

    Citing this Journal Article :

    V.sivanesan, Dr.c.christoberasir Rajan, "Design and analysis of pd-pwm multilevel inverter with reduced switch count", https://www.ijltet.org/journal_details.php?id=930&j_id=4474, Volume 10 Issue 2 - April 2018, 89-95, #ijltetorg