Volume 8 Issue 3 - May 2017

  • 1. Design and implementation of single precision floating point multiplier using vhdl on spartan 3

    Authors : Pooja Hatwalne, Ameya Deshmukh, Tanmay Paliwal, Krupal Lambat

    Pages : 263-269

    DOI : http://dx.doi.org/10.21172/1.83.040

    Keywords : single precision floating point multiplierVHDLcarry look ahead adder Vedic multiplierXilinxSpartan-3.

    Abstract :

    Floating-point arithmetic algorithms are highly useful for computations involving large dynamic range, high precision and ease of operation. Hence, they find lot of applications in the various fields for the requirements for high precision operation. This paper presents the design and implementation of single precision floating point multiplier using VHDL hardware description language. 8 bit Carry Look Ahead Adder is used for the purpose of exponent addition and 24 bit Vedic Multiplier based on Urdhva-Triyagbhyam Sutra in Vedic Mathematics is used for the purpose of Mantissa multiplication in the proposed floating point multiplier. The designs are synthesized and simulated in Xilinx ISE 14.7 targeted on xc3s50-5pq208 Spartan -3 device.

    Citing this Journal Article :

    Pooja Hatwalne, Ameya Deshmukh, Tanmay Paliwal, Krupal Lambat, "Design and implementation of single precision floating point multiplier using vhdl on spartan 3", https://www.ijltet.org/journal_details.php?id=914&j_id=3762, Volume 8 Issue 3 - May 2017, 263-269, #ijltetorg