1. Design and implementation of time efficient floating point multiplier using vhdl
Authors : Ameya Deshmukh, Pooja Hatwalne
Pages : 84-90
DOI : http://dx.doi.org/10.21172/1.83.011
Keywords : single precision floating point multiplier, VHDL, fast adders, delay, Xilinx, Spartan-3 Abstract :This paper presents the design and implementation of time efficient single precision floating point multiplier using VHDL hardware description language. Comparison of various 8 bit fast adders is done using area and delay parameters and the efficient one is used in exponent addition of floating point multiplier. Similarly, comparison of two 24 bit multipliers is done on the area and delay parameters and the efficient one is used in mantissa multiplication of floating point multiplier. All these designs are synthesized and simulated in Xilinx ISE 14.7 targeted on xc3s50-5pq208 Spartan -3 device.
Citing this Journal Article :Ameya Deshmukh, Pooja Hatwalne, "Design and implementation of time efficient floating point multiplier using vhdl", Volume 8 Issue 3 - May 2017, 84-90
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