Volume 8 Issue 2 - March 2017

  • 1. Design of low power and high speed multiplier

    Authors : Shivani Siwach, Suman Nehra

    Pages : 89-95

    DOI : http://dx.doi.org/10.21172/1.82.014

    Keywords : Multiplier, Pass Transistor logic

    Abstract :

    This paper is based on multiplier structure that has a lower power consumption as well as high speed compared with the conventional one. The reduction in power is achieved by applying Pass Transistor Logic (PTL) in Conventional Full Adder to improve the efficiency of the conventional multiplier structure. In this the full adder used in multiplier is replaced by a full adder using pass transistor Logic. The simulation of this multiplier is done using TANNER EDA. Finally, a low power and high speed proposed structure is implemented, which lowers the power consumption without considerably impacting the speed. The proposed structure is assessed by comparing their speed, power, and delay parameters with those of other existing multiplier using a 45-nm CMOS technology for a wide range of supply voltages.

    Citing this Journal Article :

    Shivani Siwach, Suman Nehra, "Design of low power and high speed multiplier", https://www.ijltet.org/journal_details.php?id=911&j_id=3663, Volume 8 Issue 2 - March 2017, 89-95, #ijltetorg