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Volume 7 Issue 1 - May 2016

  • 1. Power consumption in combination circuit by using gate diffusion input technology

    Authors : Priyanka Sharma, Udit Mamodiya

    Pages : 293-300

    DOI : http://dx.doi.org/10.21172/1.71.042

    Keywords : GDI technology, DPL CPL

    Abstract :

    ABSTRACT:　This paper presents the reduction of power consumption in 90nm full adder construction with the help of CMOS architecture, also an approach has been made to reduce the power in digital circuits by using diffusion input scheme. By this architecture concept, low power logic designs are introduced that will reduce the layout area, lesser number of devices and the most important one low power consummations. Using GDI technique (XOR logic gate full adder) as well as CMOS logic, different block has been designed to propose low power realization of FIR filters.Adders are heart of computational circuits and many complex arithmetic circuits are based on the addition. The vast use of this operation in arithmetic functions attracts a lot of researcher’s attention to adder for mobile applications. In recent years, several variants of different logic styles have been proposed to implement 1-bit adder cells. These adder cells commonly aimed to reduce power consumption and increase speed. These studies have also investigated different approaches realizing adders using CMOS technology. For mobile applications, designers have to work within a very tight leakage power specification in order to meet product battery life and package cost objectives. The designer's concern for the level of leakage current is not related to ensuring correct circuit operation, but is related to minimize power dissipation. For portable electronic devices this equates to maximizing battery life. For example, mobile phones need to be powered for extended periods (known as standby mode, during which the phone is able to receive an incoming call), but are fully active for much shorter periods (known as talk or active mode, while making a call).

    Citing this Journal Article :

    Priyanka Sharma, Udit Mamodiya, "Power consumption in combination circuit by using gate diffusion input technology", Volume 7 Issue 1 - May 2016, 293-300

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