Volume 6 Issue 3 - January 2016

  • 1. Design of 32 bit mips risc processor based on soc

    Authors : Pranjali Kelgaonkar

    Pages : 446-450

    Keywords : RISC, MIPS, Simulation Synthesis ,Instruction Set,MODELSIM.s,SOC.

    Abstract :

    This paper concerned with the design and implementation of a 32bit Reduced Instruction Set Computer (RISC) processor on a Field Programmable Gate Arrays (FPGAs). The processor has been designed with Verilog HDL, synthesized using Xilinx ISE 14.2 and simulated using QuestaSim 6.4C simulator, and then will implement on ZedBoard_HW_UG_v1_9. The project involves design of a 32bit RISC processor and simulating it. A Reduced Instruction Set compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor . We use pipeline design process to reduce the execution time of instruction successfully, which involves instruction fetch (IF), instruction decoder (ID), execution (EXE), data memory (MEM), write back (WB) modules of 32-bit RISC processor.

    Citing this Journal Article :

    Pranjali Kelgaonkar, "Design of 32 bit mips risc processor based on soc", https://www.ijltet.org/journal_details.php?id=898&j_id=2883, Volume 6 Issue 3 - January 2016, 446-450, #ijltetorg