Volume 6 Issue 3 - January 2016

  • 1. Implementation of low power bist for 32 bit vedic multiplier

    Authors : T Srinivasa Rao, V Bhatathi Devarakonda

    Pages : 6-15

    Keywords : Vedic multiplierTest Pattern GenerationMISRCUT

    Abstract :

    In this paper, low power built-in self test (BIST) is designed for 32 bit Vedic multiplier. The objective of this work is to reduce power consumption in BIST with increased fault coverage. Various methods of pattern generation are compared keeping in view of power consumption. In this test pattern generation the seed value is changed every 2m cycles. For this purpose m bit binary counter & gray code generator is used. Signature analysis is done with the help of Multiple Input Signature Register (MISR). The signature of MISR will indicate whether the circuit under test (CUT) i.e. Vedic multiplier is faulty or not. The results are tabulated and compared. From the implementation results, the low power BIST shows better power reduction than other methods. Simulation is carried out in Xilinx ISE and the design is implemented using Vertex 5 Field Programmable Gate Array (FPGA).

    Citing this Journal Article :

    T Srinivasa Rao, V Bhatathi Devarakonda, "Implementation of low power bist for 32 bit vedic multiplier", https://www.ijltet.org/journal_details.php?id=898&j_id=2814, Volume 6 Issue 3 - January 2016, 6-15, #ijltetorg