Volume 2 Issue 3 - May 2013

  • 1. A new high speed low power performance of 8- bit parallel multiplier-accumulator using modified radix-2 booth encoded algorithm

    Authors : V.sandeep Kumar, V.swathi

    Citing this Journal Article :

    V.sandeep Kumar, V.swathi, "A new high speed low power performance of 8- bit parallel multiplier-accumulator using modified radix-2 booth encoded algorithm", https://www.ijltet.org/journal_details.php?id=875&j_id=2638, Volume 2 Issue 3 - May 2013, , #ijltetorg