1. Analysis of 6t-sram cell designs using mos and fgmos for low power applications
Authors : Sneha Sharan, Anshu Chandra
Pages : 220 - 227
Keywords : MOSFGMOSWrite DelayRead DelayPower DissipationSupply Voltage Abstract :
SRAM (Static Random Access Memory) is a type of semiconductor memory that uses two cross coupled CMOS inverter to store each bit. It is the main part of cache, therefore its power dissipation reduction is the main concern. Last one decade has shown intensive research for reducing power dissipation and delay. The present work aims to reduce leakage power without affecting the logic state of SRAM cell. Power dissipation and delay, simulation in read and write operation of SRAM cell has been performed to analyze the results. Furthermore, analysis has been done for the SRAM cell by using forced stack transistor technique and sleep transistor technique. The simulation has been done using SPICE for 180nm, 90nm, 65nm, 45nm and 32nm CMOS technology nodes. The supply voltage 0.35V is used for sub threshold operation. Results indicate that use of FGMOS in place of MOS in SRAM cell reduces power dissipation and delay.
Citing this Journal Article :Sneha Sharan, Anshu Chandra, "Analysis of 6t-sram cell designs using mos and fgmos for low power applications", Volume 6 Issue 4 - March 2016, 220 - 227
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